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D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS72D32500GR-[7F/7/8]-B HYS72D64500GR-[7F/7/8]-B HYS72D1285[20/21]GR-[7F/7]-B HYS72D128521GR-8-B
Registered DDR SDRAM-Modules D D R SD R A M
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2004-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, EditionMunchen, Germany 81669 2004-01 Published by Infineon Technologies AG, (c) Infineon Technologies AG 2004. St.-Martin-Strasse 53, All Rights Reserved. 81669 Munchen, Germany Attention Technologies AG 2004. (c) Infineonplease! All Rights Reserved. The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Attention please! Terms of delivery and rights to technical change reserved. The hereby disclaim any and all to describe certain components andto warranties considered as a guarantee of We information herein is given warranties, including but not limited shall not be of non-infringement, regarding characteristics. circuits, descriptions and charts stated herein. Terms of Technologiesrights approved CECC manufacturer. Infineon delivery and is an to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Information Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide For further information on technology, delivery terms and conditions and prices please contact your nearest (www.infineon.com). Infineon Technologies Office (www.infineon.com). Warnings Warnings Due to technical requirements components may contain dangerous substances. For information on the types in Due to technical contact your nearest Infineon Technologies Office. substances. For information on the types in question please requirements components may contain dangerous question Technologies Components may only be used in life-support devices or systems with the express written Infineon please contact your nearest Infineon Technologies Office. Infineon Technologies Componentsifmay only of such components can reasonably be expected to cause the approval of Infineon Technologies, a failure be used in life-support devices or systems with the express written approval of Infineon Technologies, if system, or to affect the safetycaneffectiveness ofexpected to cause the failure failure of that life-support device or a failure of such components or reasonably be that device or system. Life of that life-support device or are intended to be implanted in the human body, that device orand/or maintain and support devices or systems system, or to affect the safety or effectiveness of or to support system. Life support devices and/or protect human life. Ifbe implanted in the human body, or to support and/or maintain or other sustain or systems are intended to they fail, it is reasonable to assume that the health of the user and sustain and/or protectbe endangered. fail, it is reasonable to assume that the health of the user or other persons may persons may human life. If they be endangered.
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H Y S 72 D 3 2 5 0 0 G R - [ 7 F / 7 / 8 ] - B HYS72D64500GR-[7F/7/8]-B HYS72D1285[20/21]GR-[7F/7]-B HYS72D128521GR-8-B
Registered DDR SDRAM-Modules D D R SD R A M
Memo P Pro t u M e m or yr y r o du cds c t s
Never
stop
thinking.
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
HYS72D32500GR-[7F/7/8]-B, HYS72D64500GR-[7F/7/8]-B, HYS72D1285[20/21]GR-[7F/7]-B Revision History: Previous Version: Page all Rev. 1.03 V.092 2004-01
Subjects (major changes since last revision) Editorial changes
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Data Sheet
4
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 18
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Sheet
5
Rev. 1.03, 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Overview
1
1.1
* * * * * * * * * *
Overview
Features
* *
184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications One rank 32M x 72, 64M x 72 and two ranks 128M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply Built with DDR SDRAMs in 66-Lead TSOPII package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 30,48 mm (1.2") x 4.00 mm (6,80 mm with stacked components) Based on JEDEC standard reference card layouts Raw Card L,M,N Gold plated contacts Performance -7F DDR266F PC2100 fCK fCK 143 133 -7 DDR266A PC2100 143 133 -8 DDR200A PC1600 125 100 Unit - - MHz MHz
Table 1
Part Number Speed Code Module Speed Grade Component Module max. Clock Frequency @ CL = 2.5 @ CL = 2
1.2
Description
The HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B are low profile versions of the standard Registered DIMM modules with 1.2" inch (30,48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 32M x 72 (256MB), 64M x 72 (512MB) and 128M x 72 (1 GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Overview
Table 2
Ordering Information Compliance Code Description SDRAM Technology 256 Mbit (x8) 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x4) 256 MBit (x4) (stacked with soldering process) 256 MBit (x4) (stacked with soldering process) 256 MBit (x4) (stacked with laser welding process) 256 MBit (x4) (stacked with laser welding process) 256 Mbit (x8) 256 Mbit (x4) 256Mbit (x4) (stacked with laser welding process)
Product Type PC2100 (CL = 2): HYS72D32500GR-7F-B HYS72D32500GR-7-B HYS72D64500GR-7F-B HYS72D64500GR-7-B HYS72D128520GR-7F-B
PC2100R-20220-L PC2100R-20330-L PC2100R-20220-M PC2100R-20330-M PC2100R-20220-N
one rank 256 MB Registered DIMM one rank 256 MB Registered DIMM one rank 512 MB Registered DIMM one rank 512 MB Registered DIMM two ranks 1 GByte Registered DIMM
HYS72D128520GR-7-B
PC2100R-20330-N
two ranks 1 GByte Registered DIMM
HYS72D128521GR-7F-B
PC2100R-20220-N
two ranks 1 GByte Registered DIMM
HYS72D128521GR-7-B
PC2100R-20330-N
two ranks 1 GByte Registered DIMM
PC1600 (CL = 2): HYS72D32500GR-8-B HYS72D64500GR-8-B HYS72D128521GR-8-B PC1600R-20220-L PC1600R-20220-M PC1600R-20220-M one rank 256 MB Registered DIMM one rank 512 MB Registered DIMM two ranks 1GByte Registered DIMM
Note: All "product type" end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D32500GR-7-B, indicating rev. C dies are used for SDRAM components. The "compliance code" is printed on the module labels describing the speed sort (for example "PC2100"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration
2
Table 3 Symbol
Pin Configuration
Pin Definitions and Functions Type Input Input Input/Output Input/Output Input Input Input Input Input/Output Input Input Input/Output Input Supply Supply Supply Output Supply Supply Input Output Input Input Input Input Function Address Inputs (A12 for 256 MB & 512 MB based modules) Bank Selects Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable SDRAM low data strobes Differential Clock Input SDRAM low data mask high data strobes Chip Selects Power (+2.5 V) Ground I/O Driver power supply
A0 - A11, A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0, CKE1 DQS0 - DQS8 CK0, CK0 DM0 - DM8 DQS9 - DQS17 CS0, CS1
VDD VSS VDDQ VDDID VDDSPD VREF
SCL SDA SA0 - SA2 NC DU RESET
VDD Indentification flag
EEPROM power supply I/O reference supply Serial bus clock Serial bus data line slave address select no connect don't use Reset pin (forces register inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the end of this datasheet
Data Sheet
8
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration Table 4 Density Address Format Organization Memory Ranks SDRAMs # of SDRAMs # of row/rank/ columns bits 13 / 2 / 10 13 / 2 / 11 13 / 2 / 11 Refresh Period Interval
256 MB 512 MB 1 GB
32M x 72 64M x 72 128M x 72
1 1 2
256Mbit 32M x 8 256Mbit 64M x 4 256Mbit 64M x 4
9 18 36 (stacked)
8K 8K 8K
64 ms 64 ms 64 ms
7.8 s 7.8 s 7.8 s
Table 5 PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Pin Configuration Symbol PIN# 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Symbol A0 CB2 PIN# 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 9 Symbol DQ4 DQ5 PIN# 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 Symbol A10 CB6
VREF
DQ0
VSS
DQ1 DQ0 DQ2
VSS
CB3 BA1 KEY DQ32
VDDQ
DM0/DQS9 DQ6 DQ7
VDDQ
CB7 KEY
VSS
DQ36 DQ37
VDD
DQ3 NC RESET
VSS
NC NC NC
VDDQ
DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
VDD
DM4/DQS13 DQ38 DQ39
VSS
DQ8 DQ9 DQS1
VDDQ
DQ12 DQ13 DM1/DQS10
VSS
DQ44 RAS DQ45
VDDQ
DU DU
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VDDQ
CS0 CS1 DM5/DQS14
VSS
DQ10 DQ11 CKE0
VDDQ
NC DQ20 NC / A12
VSS
DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS DU DU
VSS
DQ46 DQ47 NC
VDDQ
DQ16 DQ17 DQS2
VSS
DQ21 A11 DM2/DQS11
VDDQ
DQ52 DQ53 NC
VSS
A9 DQ18 A7
VDD
DQ22 A8 DQ23
VDD
DM6/DQS15 Rev. 1.03 2004-01
VDDQ
Data Sheet
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration Table 5 PIN# 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin Configuration (cont'd) Symbol DQ19 A5 DQ24 PIN# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Symbol PIN# 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Symbol PIN# 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 - - Symbol DQ54 DQ55
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VDDQ
NC DQ60 DQ61
VSS
DQ25 DQS3 A4
VSS VDDID
DQ56 DQ57
VDDQ
DM3/DQS12 A3 DQ30
VSS
DM7/DQS16 DQ62 DQ63
VDD
DQ26 DQ27 A2
VDD
DQS7 DQ58 DQ59
VSS
DQ31 CB4 CB5
VDDQ
SA0 SA1 SA2
VSS
A1 CB0 CB1
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDDSPD
- -
VDD
DQS8
VSS
DM8/DQS17
VSS
Note: A12 is used for 256Mbit and 512Mbit based modules only
Data Sheet
10
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration
RS0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D7
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
VDDSPD Serial PD SCL D8 WP A0 A1 A2 SDA SA0 SA1 SA2 VDDQ VDD VREF VSS VDDID
Serial PD D0- D8 D0-D8 D0-D8 D0-D8 Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. SDRAM placement alternates between the back and front sides of the DIMM. 6. Address and control resistors should be 22 Ohms.
S0 BA0-BA1 A0-An7 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 -> CS: SDRAMs D0-D8 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8 RA0-RAn7 -> A0-An7: SDRAMs D0-D8 RRAS -> RAS: SDRAMs D0-D8 RCAS -> CAS: SDRAMs D0-D8 RCKE0 -> CKE: SDRAMs D0- D8 RWE -> WE: SDRAMs D0-D8 CK0, CK0 --------- PLL* RESET * Wire per Clock Loading Table/Wiring Diagrams
7. A13 is not wired for raw card A.
Figure 1
Block Diagram: One Rank 32M x 72 DDR SDRAM DIMM Module (x8 components) HYS72D32500GR on Raw Card L
Data Sheet
11
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration
VSS RS0
DQS0
DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DQS9
DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
D0
D9
DQS1
DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DQS10
DQS DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
D1
D10
DQS2
S DM DQ16 DQ17 DQ18 DQ19
DQS11
S DM DQ20 DQ21 DQ22 DQ23
D2
D11
DQS3
S DM DQ24 DQ25 DQ26 DQ27
DQS12
S DM
D3
DQ28 DQ29 DQ30 DQ31
D12
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DQS13
D4
DQ36 DQ37 DQ38 DQ39 DM
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3
S
DM
VDDSPD
Serial PD D0-D17 D0-D17 D0-D17 D0-D17 Strap: see Note 4
VDDQ D13 VDD VREF
S DM
DQS5
S DQ40 DQ41 DQ42 DQ43
DQS14
VSS VDDID
D5
D14
DQS6
S DM DQ48 DQ49 DQ50 DQ51
DQS15
DQ52 DQ53 DQ54 DQ55
Serial PD
DQS S I/O 0 I/O 1 D15 I/O 2 I/O 3 S DM
SCL WP A0 A1 A2
SDA SA0 SA1 SA2
D6
DQS7
DQ56 DQ57 DQ58 DQ59 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DQS16
D7
DQ60 DQ61 DQ62 DQ63 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM
D16
DQS8
S
DQS17
CB4 CB5 CB6 CB7
S
DM
CB0 CB1 CB2 CB3
D8
D17
S0 BA0-BA1 A0-An6 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 -> CS : SDRAMs D0-D17 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17 RA0-RAn6 -> A0-An6: SDRAMs D0-D17 RRAS -> RAS: SDRAMs D0-D17 RCAS -> CAS: SDRAMs D0-D17 RCKE0A -> CKE: SDRAMs D0-D17 CK0, CK0 --------- PLL* RWE -> WE: SDRAMs D0-D17 * Wire per Clock Loading Table/Wiring Diagrams RESET
Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. Address and control resistors should be 22 Ohms. 6. A13 is not wired for raw card B.
Figure 2
Block Diagram: One Rank 64M x 72 DDR SDRAM DIMM Module (x4 components) HYS72D64500GR on Raw Card M 12 Rev. 1.03 2004-01
Data Sheet
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Pin Configuration
VSS RS1 RS0 DQS0
DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM
DM0/DQS9
D0
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQ4 DQ5 DQ6 DQ7
D18
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
S
DM
D9
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
S
DM
D27
DQS1
S DM S DM DQ8 DQ9 DQ10 DQ11
DM1/DQS10
S DM S DM
D1
D19
DQ12 DQ13 DQ14 DQ15
D10
D28
DQS2
S DM S DM DQ16 DQ17 DQ18 DQ19
DM2/DQS11
S DM S DM
D2
D20
DQ20 DQ21 DQ22 DQ23
D11
D29
DQS3
DQ24 DQ25 DQ26 DQ27
DM3/DQS12
S DM S DM DQ28 DQ29 DQ30 DQ31 S DM S DM
D3
D21
D12
D30
DQS4
DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM S DM
DM4/DQS13
D4 D22
DQ36 DQ37 DQ38 DQ39 DM
S
DM
S
DM
D13
D31
DQS5
S DM S DQ40 DQ41 DQ42 DQ43
DM5/DQS14
DQ44 DQ45 DQ46 DQ47
S
DM
DQS I/O 0 I/O 1 I/O 2 I/O 3
S
DM
D5
D23
D14
D32
DQS6
S DM I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 S DM DQ48 DQ49 DQ50 DQ51
DM6/DQS15
DQ52 DQ53 DQ54 DQ55
S
DM
D6
D15
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
S
DM
D33
DQS7
S S DM DQ56 DQ57 DQ58 DQ59
DM7/DQS16
S DM S
DM
D7
D25
DQ60 DQ61 DQ62 DQ63 DM
D16
D34
DQS8
S DM S CB0 CB1 CB2 CB3
DM8/DQS17
S DM S DM CB4 CB5 CB6 CB7
D8
D26
D17
D35
CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams S0 S1 BA0-BA1 A0-A13 RAS CAS CKE0 CKE1 WE PCK PCK
Serial PD SCL WP A0 A1 A2
VDDSPD
R E G I S T E R
RSO -> S : SDRAMs D0-D17 RS1 -> S : SDRAMs D18-D35 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35 RA0-RA13 -> A0-A13: SDRAMs D0- D35 RRAS -> RAS: SDRAMs D0-D35 RCAS -> CAS: SDRAMs D0-D35 RCKE0 -> CKE: SDRAMs D0-D17 RCKE1 -> CKE: SDRAMs D18-D35 RWE -> WE: SDRAMs D0-D35 RESET
SA0 SA1 SA2
VDDQ SDA VDD VREF VSS VDDID
Serial PD D0-D35 D0-D35 D0-D35 D0-D35 Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ. 5. Address and control resistors should be 22 Ohms. 6. Each Chip Select and CKE pair alternate between decks for thermal enhancement.
Figure 3
Block Diagram: Two Ranks 128M x 72 DDR SDRAM DIMM Modules (x4 components) HYS72D128520GR on Raw Card N 13 Rev. 1.03 2004-01
Data Sheet
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values min. max. 3.6 3.6 +150 1 50 V V
o
Unit
Input/Output voltage relative to VSS Power supply voltage on VDD/VDDQ to VSS Storage temperature range Power dissipation (per SDRAM component) Data out current (short circuit)
VIN, VOUT VDD, VDDQ TSTG PD IOS
-0.5 -0.5 -55 - -
C
W mA
Attention: Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability Table 7 Parameter Device Supply Voltage Output Supply Voltage Input Reference Voltage Termination Voltage EEPROM supply voltage Note: 1. Under all conditions, VDDQ must be less than or equal to VDD 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 3. VTT of the transmitting device must track VREF of the receiving device . Table 8 Parameter DC Input Logic High DC Input Logic Low Input Leakage Current Output Leakage Current Note: 1. The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max.) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). 2. For any pin under test input of 0 V VIN VDDQ + 0.3 V. Values are shown per DDR-SDRAM component Data Sheet 14 Rev. 1.03 2004-01 DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 C, Voltage Referenced to VSS)
Supply Voltage Levels Symbol Values min. nom. 2.5 2.5 0.5 x VDDQ max. 2.7 2.7 0.51 x VDDQ 2.3 2.3 0.49 x VDDQ Unit/ Notes V V 1) V 2) V 3) V
VDD VDDQ VREF VTT VDDSPD
VREF - 0.04
2.3
VREF
2.5
VREF + 0.04
3.6
Symbol
Values min. max.
Unit/ Notes
V 1)
VIH, (DC) VIL, (DC) IIL IOL
VREF +0.15
-0.30 -5 -5
VDDQ +0.3 VREF -0.15
5 5
V
A 1) A 2)
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
3.2
Table 9 Parameter
Current Specification and Conditions
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
15
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
Table 10
IDD Specifications -7F/-7
HYS72D128521GR-7F-B HYS72D128520GR-7F-B HYS72D32500GR-7F-B HYS72D64500GR-7F-B HYS72D128520GR-7-B HYS72D128521GR-7-B Unit HYS72D32500GR-7-B HYS72D64500GR-7-B Note/ Test Conditions5)
Product Type & Organisation
256 MB 512 MB 1 GByte 1 GByte 256 MB 512 MB 1 GByte 1 GByte x72 -7F max. 990 1080 72 360 225 162 495 1035 1125 1620 23 2025 x72 -7F max. 1980 2160 144 720 450 324 990 2070 2250 3240 45 4050 x72 -7F max. 2970 3150 288 1440 900 648 1980 3060 3240 4230 90 5040 x72 -7F max. 2970 3150 288 1440 900 648 1980 3060 3240 4230 90 5040 x72 -7 max. 900 990 72 360 225 162 495 1035 1125 1620 23 2025 x72 1 Rank -7 max. 1800 1980 144 720 450 324 990 2070 2250 3240 45 4050 x72 -7 max. 2790 2970 288 1440 900 648 1980 3060 3240 4230 90 5040 x72 -7 max. 2790 2970 288 1440 900 648 1980 3060 3240 4230 90 5040 mA mA mA mA mA mA mA mA mA mA mA mA
1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5)
1 Rank 1 Rank
2 Ranks 2 Ranks 1 Rank
2 Ranks 2 Ranks
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) DRAM component currents only: module currents
IDD will be measured differently depending upon register and PLL operation
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C
Data Sheet
16
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
Table 11
IDD Specifications -8
HYS72D128521GR-8-B HYS72D32500GR-8-B HYS72D64500GR-8-B Unit Note/ Test Conditions5)
Product Type & Organisation
256 MB x72 1 Rank -8 max. 810 900 63 315 198 144 405 855 945 1530 22,5 1890
512 MB x72 1 Rank -8 max. 1620 1800 126 630 396 288 810 1710 1890 3060 45 3780
1 GByte x72 2 Ranks -8 max. 2430 2610 252 1260 792 576 1620 2520 2700 3870 90 4590 mA mA mA mA mA mA mA mA mA mA mA mA
1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) DRAM component currents only: module currents
IDD will be measured differently depending upon register and PLL operation
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C
Data Sheet
17
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
3.3
Table 12 Parameter
AC Characteristics
AC Timing - Absolute Specifications -8/-7/-7F Symbol -8 DDR200 Min. Max. Min. -7 DDR266A Max. -0.75 +0.75 -0.75 +0.75 0.45 0.45 7 7.5 0.5 0.5 2.2 1.75 0.55 0.55 12 12 -- -- -- -- -7F DDR266F Min. Max. - +0.75 0.75 - +0.75 0.75 0.45 0.55 0.45 0.55 7 7.5 0.5 0.5 2.2 12 12 -- -- -- Unit Note/ Test Condition 1) ns ns
2)3)4)5)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle)
tAC tDQSCK tCH tCL tHP tCK2.5 tCK2 tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ tQHS tQH tDQSL,H tDSS
-0.8 +0.8 -0.8 +0.8 0.45 0.55 0.45 0.55 min. (tCL, tCH) 8 10 0.6 0.6 2.5 2.0 12 12 -- -- -- --
2)3)4)5)
tCK tCK
ns ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
1.75 -- - +0.75 0.75 - +0.75 0.75 0.75 1.25 -- -- +0.5 0.75
2)3)4)5)6)
-0.8 +0.8 -0.8 +0.8 0.75 1.25 -- -- +0.6 1.0
-0.75 +0.75 -0.75 +0.75 0.75 -- -- 1.25 +0.5 0.75 -- -- -- -- -- -- 0.60 --
2)3)4)5)7)
2)3)4)5)7)
tCK
ns ns ns ns ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
tHP - -- tQHS
0.35 -- 0.2 0.2 2 0 -- -- -- --
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25
tHP - -- tQHS
0.35 -- 0.2 0.2 2 0 -- -- -- --
2)3)4)5)
tCK tCK tCK tCK
ns
2)3)4)5)
2)3)4)5)
DQS falling edge hold time from tDSH CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble
2)3)4)5)
tMRD tWPRES tWPST tWPRE
2)3)4)5)
2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
0.40 0.60 0.25 --
0.40 0.60 0.25 --
tCK tCK
Data Sheet
18
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics Table 12 Parameter AC Timing - Absolute Specifications -8/-7/-7F Symbol -8 DDR200 Min. Max. Address and control input setup tIS time 1.1 1.1 Address and control input hold time -- -- -- -- 1.1 -- Min. 0.9 1.0 0.9 1.0 0.9 NA 0.40 65 75 20 20 20 15 15 0.60 -- -- -- -- -- -- -- -7 DDR266A Max. -- -- -- -- 1.1 -7F DDR266F Min. Max. 0.9 1.0 0.9 1.0 0.9 NA 120E+3 45 65 75 20 20 20 15 15 -- -- -- -- 1.1 -- Unit Note/ Test Condition 1) ns ns ns ns fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
tIH
1.1 1.1
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Read preamble Read preamble setup time Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Autorefresh command period Active to Read or Write delay
tRPRE tRPRES tRPST tRAS tRC tRFC
0.9 1.5 50 70 80 20 20 20 15 15
tCK tCK
ns ns ns ns ns ns ns ns
CL > 1.5 2)3)4)5)
2)3)4)5)11) 2)3)4)5) 2)3)4)5) 2)3)4)5)
0.40 0.60 -- -- -- -- -- -- --
0.40 0.60 -- -- -- -- -- -- --
120E+3 45
120E+3 tCK
2)3)4)5)
tRCD Precharge command period tRP Active to Autoprecharge delay tRAP Active bank A to Active bank B tRRD
command
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tWR Auto precharge write recovery + tDAL
Write recovery time precharge time Internal write to read command tWTR delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
2)3)4)5) 2)3)4)5)12)
(twr/tCK) + (trp/tCK) 1 80 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tCK tCK ns tCK
s
CL > 1.5 2)3)4)5)
2)3)4)5)
tXSNR tXSRD tREFI
2)3)4)5)
2)3)4)5)13)
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V 2) Input slew rate 1 V/ns for DDR266a, DDR266F and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
19
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Electrical Characteristics
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) tRPRES is defined for CL = 1.5 operation only 12) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents
4
Table 13
SPD Contents
SPD Codes for HYS72D32500GR-[7F/7/8]-B HYS72D32500GR-7F-B x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C0 75 75 00 Rev. 1.03 2004-01 HYS72D32500GR-8-B HYS72D32500GR-7-B x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 26 C0 75 75 00
Product Type & Organization
x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 80 08 07 0D 0A 01 48 00 04 80 80 02 82 08 08 01 0E 04 0C 01 02 26 C0 A0 80 00
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
21
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 13 SPD Codes for HYS72D32500GR-[7F/7/8]-B HYS72D32500GR-7F-B x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 00 3C 3C 3C 2D 40 90 90 50 50 00 3C 4B 30 32 75 00 00 00 00 9D C1 49 4E 46 49 4E Rev. 1.03 2004-01 HYS72D32500GR-8-B HYS72D32500GR-7-B x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 CA C1 49 4E 46 49 4E
Product Type & Organization
x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 00 50 3C 50 32 40 B0 B0 60 60 00 46 50 30 3C A0 00 00 00 00 BF C1 49 4E 46 49 4E
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46 47 48-61 62 63 64 65 66 67 68 69 Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6)
Data Sheet
22
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 13 SPD Codes for HYS72D32500GR-[7F/7/8]-B HYS72D32500GR-7F-B x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 45 4F xx 37 32 44 33 32 35 30 30 47 52 37 46 42 20 20 20 20 20 xx xx xx xx xx xx Rev. 1.03 2004-01 HYS72D32500GR-8-B HYS72D32500GR-7-B x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 45 4F xx 37 32 44 33 32 35 30 30 47 52 37 42 20 20 20 20 20 20 xx xx xx xx xx xx
Product Type & Organization
x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 45 4F xx 37 32 44 33 32 35 30 30 47 52 38 42 20 20 20 20 20 20 xx xx xx xx xx xx
Label Code Jedec SPD Revision Byte# 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Description JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2)
Data Sheet
23
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 13 SPD Codes for HYS72D32500GR-[7F/7/8]-B HYS72D32500GR-7F-B x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX xx xx 00 x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 80 08 07 0D 0B 01 Rev. 1.03 2004-01 HYS72D64500GR-8-B HYS72D32500GR-8-B HYS72D32500GR-7-B x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX xx xx 00 x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 80 08 07 0D 0B 01 HYS72D64500GR-7-B
Product Type & Organization
x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX xx xx 00
Label Code Jedec SPD Revision Byte# 97 98 99-127 Description Module Serial Number (3) Module Serial Number (4) not used
Table 14
SPD Codes for HYS72D64500GR-[7F/7/8]-B HYS72D64500GR-7F-B x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 80 08 07 0D 0B 01 24
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks
Data Sheet
Product Type & Organization
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 14 SPD Codes for HYS72D64500GR-[7F/7/8]-B HYS72D64500GR-7F-B HYS72D64500GR-7-B HYS72D64500GR-8-B x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 48 00 04 80 80 02 82 04 04 01 0E 04 0C 01 02 26 C0 A0 80 00 00 50 3C 50 32 80 B0 Rev. 1.03 2004-01
Product Type & Organization
x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00 3C 3C 3C 2D 80 90
x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00 50 3C 50 2D 80 90
Label Code Jedec SPD Revision Byte# 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns]
Data Sheet
25
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 14 SPD Codes for HYS72D64500GR-[7F/7/8]-B HYS72D64500GR-7F-B HYS72D64500GR-7-B HYS72D64500GR-8-B x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX B0 60 60 00 46 50 30 3C A0 00 00 00 00 F8 C1 49 4E 46 49 4E 45 4F xx 37 32 44 36 Rev. 1.03 2004-01
Product Type & Organization
x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 90 50 50 00 3C 4B 30 32 75 00 00 00 00 D6 C1 49 4E 46 49 4E 45 4F xx 37 32 44 36
x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 90 50 50 00 41 4B 30 32 75 00 00 00 00 03 C1 49 4E 46 49 4E 45 4F xx 37 32 44 36
Label Code Jedec SPD Revision Byte# 33 34 35 36-40 41 42 43 44 45 46 47 48-61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Description tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4
Data Sheet
26
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 14 SPD Codes for HYS72D64500GR-[7F/7/8]-B HYS72D64500GR-7F-B HYS72D64500GR-7-B HYS72D64500GR-8-B x72 1 rank reg PC1600R - 20220 Rev. 0.0 HEX 34 35 30 30 47 52 38 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00 Rev. 1.03 2004-01
Product Type & Organization
x72 1 rank reg PC2100R - 20220 Rev. 0.0 HEX 34 35 30 30 47 52 37 46 42 20 20 20 20 20 xx xx xx xx xx xx xx xx 00
x72 1 rank reg PC2100R - 20330 Rev. 0.0 HEX 34 35 30 30 47 52 37 42 20 20 20 20 20 20 xx xx xx xx xx xx xx xx 00
Label Code Jedec SPD Revision Byte# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99-127 Description Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) not used
Data Sheet
27
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents
Table 15
SPD Codes for HYS72D1285[20/21]GR[-7F/7]-B, HYS72D128521GR-8 HYS72D128520GR-7F-B HYS72D128521GR-7F-B x72 2 Ranks reg PC2100R20220-N HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00 Rev. 1.03 2004-01 HYS72D128520GR-7-B HYS72D128521GR-8-B HYS72D128521GR-7-B x72 2 Ranks reg PC2100R20330-N HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00
Part Number & Organization
x72 2 Ranks reg PC2100R20330-N HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00 28
x72 2 Ranks reg PC2100R20220-N HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00
x72 2 Ranks reg PC1600R20220-N HEX 80 08 07 0D 0B 02 48 00 04 80 80 02 82 04 04 01 0E 04 0C 01 02 26 C0 A0 80 00 00
Label Code Jedec SPD Revision Byte# Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns]
Data Sheet
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 15 SPD Codes for HYS72D1285[20/21]GR[-7F/7]-B, HYS72D128521GR-8 HYS72D128520GR-7F-B HYS72D128521GR-7F-B x72 2 Ranks reg PC2100R20220-N HEX 3C 3C 3C 2D 80 90 90 50 50 00 00 00 00 00 3C 4B 30 32 75 00 00 00 00 D7 C1 49 4E Rev. 1.03 2004-01 HYS72D128520GR-7-B HYS72D128521GR-8-B HYS72D128521GR-7-B x72 2 Ranks reg PC2100R20330-N HEX 50 3C 50 2D 80 90 90 50 50 00 00 00 00 00 41 4B 30 32 75 00 00 00 00 04 C1 49 4E
Part Number & Organization
x72 2 Ranks reg PC2100R20330-N HEX 50 3C 50 2D 80 90 90 50 50 00 00 00 00 00 41 4B 30 32 75 00 00 00 00 04 C1 49 4E
x72 2 Ranks reg PC2100R20220-N HEX 3C 3C 3C 2D 80 90 90 50 50 00 00 00 00 00 3C 4B 30 32 75 00 00 00 00 D7 C1 49 4E
x72 2 Ranks reg PC1600R20220-N HEX 50 3C 50 32 80 B0 B0 60 60 00 00 00 00 00 46 50 30 3C A0 00 00 00 00 F9 C1 49 4E
Label Code Jedec SPD Revision Byte# Description 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 62 63 64 65 66 tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used not used not used not used not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3)
48-61 not used
Data Sheet
29
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 15 SPD Codes for HYS72D1285[20/21]GR[-7F/7]-B, HYS72D128521GR-8 HYS72D128520GR-7F-B HYS72D128521GR-7F-B x72 2 Ranks reg PC2100R20220-N HEX 46 49 4E 45 4F xx 37 32 44 31 32 38 35 32 31 47 52 37 46 42 20 20 20 20 xx xx xx Rev. 1.03 2004-01 HYS72D128520GR-7-B HYS72D128521GR-8-B HYS72D128521GR-7-B x72 2 Ranks reg PC2100R20330-N HEX 46 49 4E 45 4F xx 37 32 44 31 32 38 35 32 31 47 52 37 42 20 20 20 20 20 xx xx xx
Part Number & Organization
x72 2 Ranks reg PC2100R20330-N HEX 46 49 4E 45 4F xx 37 32 44 31 32 38 35 32 30 47 52 37 42 20 20 20 20 20 xx xx xx
x72 2 Ranks reg PC2100R20220-N HEX 46 49 4E 45 4F xx 37 32 44 31 32 38 35 32 31 47 52 37 46 42 20 20 20 20 xx xx xx
x72 2 Ranks reg PC1600R20220-N HEX 46 49 4E 45 4F xx 37 32 44 31 32 38 35 32 31 47 52 38 42 20 20 20 20 20 xx xx xx
Label Code Jedec SPD Revision Byte# Description 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year
Data Sheet
30
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
SPD Contents Table 15 SPD Codes for HYS72D1285[20/21]GR[-7F/7]-B, HYS72D128521GR-8 HYS72D128520GR-7F-B HYS72D128521GR-7F-B x72 2 Ranks reg PC2100R20220-N HEX xx xx xx xx xx 00 Rev. 1.03 2004-01 HYS72D128520GR-7-B HYS72D128521GR-8-B HYS72D128521GR-7-B x72 2 Ranks reg PC2100R20330-N HEX xx xx xx xx xx 00
Part Number & Organization
x72 2 Ranks reg PC2100R20330-N HEX xx xx xx xx xx 00
x72 2 Ranks reg PC2100R20220-N HEX xx xx xx xx xx 00
x72 2 Ranks reg PC1600R20220-N HEX xx xx xx xx xx 00
Label Code Jedec SPD Revision Byte# Description 94 95 96 97 98 99127 Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) not used
Data Sheet
31
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 4 MAX. A
4 0.1
1)
0.15 A B C
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
30.48 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 4 Package Outlines Raw Card L (L-DIM-184-13)
Data Sheet
32
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
1)
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
30.48 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 5 Package Outlines Raw Card M (L-DIM-184-12)
Data Sheet
33
Rev. 1.03 2004-01
17.8
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 6.81 MAX.
A
1)
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
30.48 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 6 Package Outlines Raw Card N (L-DIM-184-14)
Data Sheet
34
Rev. 1.03 2004-01
17.8
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 16 RESET Truth Table Register Inputs RESET H H H H L CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Register Outputs Data out (Q) H L Qo Illegal input conditions L
X: Don't care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
35
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
36
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Application Note inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b.The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
37
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR-[7F/7/8]-B Registered DDR SDRAM-Modules
Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Data Sheet
38
Rev. 1.03 2004-01
www.infineon.com
Published by Infineon Technologies AG

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